EPM3512AFC256-10N vs EPM3512AFC256-5C Perbandingan

Perbandingan bersamaan detil EPM3512AFC256-10N dari Altera dan EPM3512AFC256-5C dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3512AFC256-10N EPM3512AFC256-5C
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10000 10,000
User I/O Pins 208 212 (max)
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] —
Operating Frequency (fMAX) [DATA_NEEDED: fMAX MHz] —
Pin-to-Pin Delay (tPD) 10 ns 5 ns
Setup Time (tSU) 4.5 ns —
VCCINT (Core Supply) 3.3 V —
VCCIO (I/O Supply) 3.3 V or 2.5 V —
Technology CMOS EEPROM-based, non-volatile EEPROM-based macrocell, non-volatile
Operating Temperature (Commercial) 0 C to +70 C —
Paket 256-ball FBGA (17 mm x 17 mm) 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch
ISP Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
Tipe Mounting Surface Mount (BGA) Surface Mount
Level MSL [DATA_NEEDED: MSL rating] —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — CPLD (Complex Programmable Logic Device)
Maximum Operating Frequency — 95.2 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
Suhu Kerja — 0 °C to +70 °C (commercial, "C" grade)
Programming Interface — IEEE Std. 1532 / JTAG (4-wire) in-system programmable

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