EPM3512AFC256-7N vs EPM3512AFC256-7 Comparison

Detailed side-by-side comparison of EPM3512AFC256-7N by Altera and EPM3512AFC256-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-7N EPM3512AFC256-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10,000
User I/Os 208 —
Logic Blocks 16 (32 macrocells each) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 116.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
5V Tolerant I/O Yes —
In-System Programmability IEEE Std. 1532 compliant —
Programming Interface JTAG (IEEE 1149.1) —
Process Technology CMOS EEPROM, 0.30 um —
Package 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch 256-ball FineLine BGA (FBGA-256)
Operating Temperature 0 C to 70 C (commercial) [DATA_NEEDED: operating temperature grade]
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
User I/O Pins — 212
Pin-to-Pin Logic Delay — 7.5 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.0 V to 3.6 V (3.3 V typ.)
I/O Voltage (VCCIO) — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming — EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant)
Configuration Memory — Non-volatile EEPROM

Datasheets & Resources

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