EPM3512AFC256-7N vs EPM3512AFI256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256-7N by Altera and EPM3512AFI256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-7N EPM3512AFI256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Usable Gates 10,000 Up to 10,000
User I/Os 208 —
Logic Blocks 16 (32 macrocells each) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 116.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V 3.3 V (3.0 V to 3.6 V)
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V 2.5 V or 3.3 V (5.0 V tolerant inputs)
5V Tolerant I/O Yes —
In-System Programmability IEEE Std. 1532 compliant Yes - IEEE Std 1532 compliant
Programming Interface JTAG (IEEE 1149.1) —
Process Technology CMOS EEPROM, 0.30 um —
Package 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch 256-ball FineLine BGA (FBGA-256)
Operating Temperature 0 C to 70 C (commercial) —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Series — EPM3512
Device Type — CPLD (Complex Programmable Logic Device)
Architecture — CMOS EEPROM-based, MAX architecture
Number of Macrocells — 512
Number of Logic Array Blocks (LABs) — 16
Number of User I/O — 208
Total Pins — 256
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
MultiVolt I/O Support — 5.0 V / 3.3 V / 2.5 V
JTAG Boundary Scan — Yes - IEEE 1149.1
Program Memory — EEPROM (non-volatile)
Operating Temperature Range — -40 °C to +85 °C (industrial)
Speed Grade — -10 (10 ns tPD)

Datasheets & Resources

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