EPM3512AFC256-7N vs EPM3512AFI256-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-7N sa pamamagitan ng Altera at EPM3512AFI256-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoleteAltera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM3512AFC256-7N | EPM3512AFI256-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | Up to 10,000 |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | Yes - IEEE Std 1532 compliant |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Process Technology | CMOS EEPROM, 0.30 um | — |
| Packhaging | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FineLine BGA (FBGA-256) |
| Temperature na Operasyon | 0 C to 70 C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | EPM3512 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| Hanay ng Temperature na Operasyon | — | -40 °C to +85 °C (industrial) |
| Speed Grade | — | -10 (10 ns tPD) |