EPM3512AFC256C vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3512AFC256C by Intel and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Last Time Buy
Specification Comparison
| Parameter | EPM3512AFC256C | EPM3512AFC256-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/Os | 208 | — |
| Dedicated Input Pins | 12 | — |
| Package | 256-ball FineLine BGA (FC) | 256-pin FBGA |
| Operating Temperature | 0C to +70C (Commercial) | — |
| Speed Grade | C (per datasheet ordering code) | — |
| Configuration Technology | EEPROM (non-volatile, instant-on) | — |
| Core Voltage | 3.3 V | — |
| I/O Standards Supported | MultiVolt: 5.0 V, 3.3 V, 2.5 V | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| PCI Compliance | PCI SIG Local Bus Specification Revision 2.2 | — |
| Programming | In-system programmable via JTAG | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Mounting Type | Surface Mount | Surface Mount |
| Usable Gates | — | 10,000 |
| Maximum I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Operating Temperature Range | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin Count | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |