EPM3512AQ208-10N vs EPM3512AQC208-10S Comparison
Detailed side-by-side comparison of EPM3512AQ208-10N by Altera and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
EPM3512AQ208-10N ✓ Active
Specification Comparison
| Parameter | EPM3512AQ208-10N | EPM3512AQC208-10S |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 1750 |
| User I/Os | 172 | 208 |
| Logic Array Blocks (LABs) | 32 | 32 (16 macrocells each) |
| Package | 208-pin PQFP | 208-pin FineLine BGA-256 |
| Speed Grade | -10 (10 ns pin-to-pin delay) | -10 (tPD1 = 7.5 ns) |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) | — |
| Maximum Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V | — |
| Process Technology | CMOS EEPROM | EEPROM-based CMOS |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP | — |
| Operating Temperature (Industrial) | -40 C to +85 C | — |
| Mounting Type | Surface Mount | — |
| RoHS Status | unknown | [DATA_NEEDED: rohs_status] |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Operating Temperature | — | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |