EPM3512AQC208-10N vs EPM3512AQC208-3 Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3512AQC208-3
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $42.80 $27.80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates Up to 10,000 β€”
Logic Array Blocks (LABs) 16 16 (32 macrocells each)
User I/Os 172 β€”
Package 208-pin PQFP (Plastic Quad Flat Pack) PQFP-208
Supply Voltage 3.3 V β€”
Pin-to-Pin Delay 4.5 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz β€”
Speed Grade -10 -3
Process Technology CMOS EEPROM β€”
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant β€”
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) β€”
Operating Temperature 0 C to 70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: confirm from datasheet]
Maximum User I/O Pins β€” 172
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Bank Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (multiVolt)
In-System Programmability β€” Yes (IEEE Std. 1532 compliant)
Boundary-Scan Test β€” Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles β€” 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration β€” Yes (EEPROM-based)
Mounting Type β€” Surface Mount
MSL Level β€” [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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