EPM3512AQC208-10N vs EPM3512AQC208-3 Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3512AQC208-3
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates Up to 10,000 —
Logic Array Blocks (LABs) 16 16 (32 macrocells each)
User I/Os 172 —
Package 208-pin PQFP (Plastic Quad Flat Pack) PQFP-208
Supply Voltage 3.3 V —
Pin-to-Pin Delay 4.5 ns (-10 speed grade) —
Maximum Internal Frequency 227.3 MHz —
Speed Grade -10 -3
Process Technology CMOS EEPROM —
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant —
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) —
Operating Temperature 0 C to 70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: confirm from datasheet]
Maximum User I/O Pins — 172
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Bank Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multiVolt)
In-System Programmability — Yes (IEEE Std. 1532 compliant)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles — 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration — Yes (EEPROM-based)
Mounting Type — Surface Mount
MSL Level — [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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