EPM3512AQC208-10S vs EPM3512AQC208-10-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10S by Altera and EPM3512AQC208-10-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10S EPM3512AQC208-10-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $31.20
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates 1750 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) β€”
Package 208-pin FineLine BGA-256 208-pin PQFP (Plastic Quad Flat Pack)
User I/Os 208 172
Speed Grade -10 (tPD1 = 7.5 ns) β€”
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) β€”
Supply Voltage - VCCINT (internal) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) β€”
Programming Technology CMOS EEPROM β€”
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) β€”
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) β€”
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial)
Boundary-Scan (JTAG) Yes (1149.1 compliant) Yes, IEEE 1149.1
Program/Erase Endurance 100 cycles minimum β€”
Logic Family CMOS β€”
Process Technology EEPROM-based CMOS CMOS EEPROM
RoHS Status [DATA_NEEDED: rohs_status] β€”
Logic Elements / LABs β€” 16 Logic Array Blocks
Propagation Delay (tPD) β€” 10 ns (-10 speed grade)
Maximum Frequency (fCNT) β€” 87 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V
In-System Programmability β€” Yes, IEEE Std. 1532 compliant
PCI-SIG Compliance β€” PCI Local Bus Specification Rev 2.2 (at -10 speed grade)
Mounting Type β€” Surface Mount
Lead-Free / RoHS β€” [DATA_NEEDED: RoHS status]

Datasheets & Resources

Browse All Products Create BOM Request Quote