EPM3512AQC208-15N vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-15N by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-15N EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N - 512-Macro CPLD MAX 3000A PQFP-208 | Altera

EPM3512AQC208-15N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-15N EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macro Cells 512 —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 172 —
Typical Usable Gates 12,000 —
Number of Logic Elements 512 —
Pin-to-Pin Delay (tPD) 15 ns —
Operating Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V (MultiVolt) —
Programmable I/O Standards LVTTL, LVCMOS, PCI (with external resistor) —
In-System Programmability Yes (IEEE Std. 1532 compliant) —
Configuration Memory EEPROM (non-volatile) —
JTAG Support Yes (BST/Boundary-Scan Test) —
Package PQFP-208 (QC208) 208-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount —
Operating Temperature 0C to +70C (commercial) 0 C to 70 C (commercial)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status not in verified web data]
Macrocells — 512
Usable Gates — Up to 10,000
User I/Os — 172
Supply Voltage — 3.3 V
Pin-to-Pin Delay — 4.5 ns (-10 speed grade)
Maximum Internal Frequency — 227.3 MHz
Speed Grade — -10
Process Technology — CMOS EEPROM
In-System Programming — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
I/O Standards — MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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