EPM3512AQC208-3N vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-3N by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-3N EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.40 $42.80
Family MAX 3000A MAX 3000A
Macrocells 512 512
User I/O Pins 172 β€”
Logic Array Blocks (LABs) 16 16
Macrocells per LAB 32 β€”
Pin-to-Pin Logic Delay 3 ns (speed grade -3) β€”
Global Clock Setup Time [DATA_NEEDED: actual tSU at 3 ns grade] β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) β€”
Operating Temperature 0C to +70C (commercial) 0 C to 70 C (commercial)
Package PQFP-208 208-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount β€”
Programming Technology EEPROM (non-volatile, in-system programmable) β€”
JTAG / Boundary Scan IEEE 1149.1 compliant β€”
ISP Compliance IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: not stated in retrieved snippets] [DATA_NEEDED: RoHS status not in verified web data]
Lead-Free / Halogen-Free [DATA_NEEDED] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” Up to 10,000
User I/Os β€” 172
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
Speed Grade β€” -10
Process Technology β€” CMOS EEPROM
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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