EPM5016DC-15 vs EPM5016LC-17 Comparison
Detailed side-by-side comparison of EPM5016DC-15 by Altera and EPM5016LC-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5016DC-15 | EPM5016LC-17 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | 7 |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 12.75 V | — |
| Operating Temperature | 0 °C to 70 °C (commercial) | [DATA_NEEDED: temperature grade] |
| Package | Ceramic DIP-24 (windowed) | Windowed Ceramic DIP (LC) |
| Mounting Type | Through-Hole | — |
| Process Technology | CMOS EPROM | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| RoHS Status | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: RoHS compliance] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 EPLD |
| Technology | — | CMOS, UV-erasable |
| Product Terms | — | 160 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 17 ns |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |