EPM5016DC-15 vs EPM5016LC-17 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016DC-15 sa pamamagitan ng Altera at EPM5016LC-17 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016DC-15 | EPM5016LC-17 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 2 | — |
| Dedicated Inputs | 4 | 7 |
| User I/O Pins | 12 | — |
| Pin-to-Pin Delay (tpd) | 15 ns | — |
| Maximum Frequency (fmax) | 71 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 12.75 V | — |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | [DATA_NEEDED: temperature grade] |
| Packhaging | Ceramic DIP-24 (windowed) | Windowed Ceramic DIP (LC) |
| Uri ng Pagpapasok | Through-Hole | — |
| Process Technology | CMOS EPROM | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant] | [DATA_NEEDED: RoHS compliance] |
| Lead Finish | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 EPLD |
| Technology | — | CMOS, UV-erasable |
| Product Terms | — | 160 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 17 ns |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |