EPM5032DC-2 vs EPM5016DC-17 Comparison

Detailed side-by-side comparison of EPM5032DC-2 by Altera and EPM5016DC-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC-2 EPM5016DC-17
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.75 $16.20
Product Type CPLD (Complex Programmable Logic Device) β€”
Series MAX 5000 β€”
Macrocells 32 16
Usable Gates (typical) 600 β€”
Logic Array Blocks (LABs) 4 β€”
Package 20-pin CDIP (Ceramic DIP) Ceramic DIP-24 (DC suffix)
Speed Grade -2 (tPD ~25 ns, commercial) β€”
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) On-chip EEPROM (non-volatile)
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V
Operating Temperature 0C to +70C (commercial grade) 0C to +70C (commercial)
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) β€”
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP β€”
Interconnect Programmable Interconnect Array (PIA) with deterministic timing β€”
RoHS Status [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: confirmed compliance status from manufacturer]
Mounting Type Through-Hole (DIP) Through-hole
MSL Level Not applicable (through-hole hermetic ceramic) β€”
Family β€” MAX 5000
Logic Elements β€” [DATA_NEEDED: LE count for MAX 5000 family]
User I/O Pins (max) β€” 24
Propagation Delay (tPD) β€” 17 ns
Counter Frequency (fCNT) β€” 67 MHz
I/O Standard β€” TTL-compatible
Process Technology β€” 0.75 micron CMOS EEPROM
Pin Count β€” 24
In-System Programmability β€” Yes (ByteBlaster / BitBlaster)

Datasheets & Resources

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