EPM5032DC-2 vs EPM5016DC-17 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC-2 sa pamamagitan ng Altera at EPM5016DC-17 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DC-2 EPM5016DC-17
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Series MAX 5000 —
Macrocells 32 16
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
Packhaging 20-pin CDIP (Ceramic DIP) Ceramic DIP-24 (DC suffix)
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) On-chip EEPROM (non-volatile)
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V
Temperature na Operasyon 0C to +70C (commercial grade) 0C to +70C (commercial)
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
Tindminan RoHS [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: confirmed compliance status from manufacturer]
Uri ng Pagpapasok Through-Hole (DIP) Through-hole
Level ng MSL Not applicable (through-hole hermetic ceramic) —
Family — MAX 5000
Logic Elements — [DATA_NEEDED: LE count for MAX 5000 family]
User I/O Pins (max) — 24
Propagation Delay (tPD) — 17 ns
Counter Frequency (fCNT) — 67 MHz
I/O Standard — TTL-compatible
Process Technology — 0.75 micron CMOS EEPROM
Bilang ng Pin — 24
In-System Programmability — Yes (ByteBlaster / BitBlaster)

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