EPM5032DC-2 vs EPM5016DC-17 Vergleich

Detaillierter Direktvergleich von EPM5032DC-2 von Altera und EPM5016DC-17 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5032DC-2 EPM5016DC-17
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,75 $16,20
Product Type CPLD (Complex Programmable Logic Device) —
Series MAX 5000 —
Macrocells 32 16
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
Gehäuse 20-pin CDIP (Ceramic DIP) Ceramic DIP-24 (DC suffix)
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) On-chip EEPROM (non-volatile)
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V
Betriebstemperatur 0C to +70C (commercial grade) 0C to +70C (commercial)
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
RoHS-Status [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: confirmed compliance status from manufacturer]
Montageart Through-Hole (DIP) Through-hole
MSL-Level Not applicable (through-hole hermetic ceramic) —
Family — MAX 5000
Logic Elements — [DATA_NEEDED: LE count for MAX 5000 family]
User I/O Pins (max) — 24
Propagation Delay (tPD) — 17 ns
Counter Frequency (fCNT) — 67 MHz
I/O Standard — TTL-compatible
Process Technology — 0.75 micron CMOS EEPROM
Pin-Anzahl — 24
In-System Programmability — Yes (ByteBlaster / BitBlaster)

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