EPM5032DC-2 vs EPM5032DC-15 Comparison

Detailed side-by-side comparison of EPM5032DC-2 by Altera and EPM5032DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC-2 EPM5032DC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.75 $9.95
Product Type CPLD (Complex Programmable Logic Device) β€”
Series MAX 5000 β€”
Macrocells 32 32
Usable Gates (typical) 600 β€”
Logic Array Blocks (LABs) 4 β€”
Package 20-pin CDIP (Ceramic DIP) CERDIP-28 (windowed, through-hole)
Speed Grade -2 (tPD ~25 ns, commercial) β€”
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) β€”
Supply Voltage (VCC) 5 V (single supply, +/-5%) 5 V (nominal)
Operating Temperature 0C to +70C (commercial grade) 0C to +70C (commercial)
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) β€”
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP β€”
Interconnect Programmable Interconnect Array (PIA) with deterministic timing β€”
RoHS Status [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: RoHS status]
Mounting Type Through-Hole (DIP) Through-Hole (DIP)
MSL Level Not applicable (through-hole hermetic ceramic) β€”
Family β€” MAX 5000
Device Type β€” UV-erasable EPLD (PAL-type CMOS)
Usable Gates β€” 600
Propagation Delay (tPD) β€” 15 ns
Maximum Toggle Frequency (fMAX) β€” 83.3 MHz
Logic Family β€” CMOS, TTL-compatible I/O
Programmable Pins β€” 16 bidirectional I/O + 4 dedicated input = 20
Total Package Pins β€” 28
Erasure Method β€” UV light through ceramic quartz window
Process Technology β€” CMOS
Lead-Free β€” unknown

Datasheets & Resources

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