Altera

EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28

Name: EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
Brand: Altera
SKU: EPM5032DC-15
Price: 9.95 USD
Availability: InStock

MPN: EPM5032DC-15 ✗ End of Life

In Stock Ships in 1-3 business days

5 V (nominal) Vdss 28 Package 83.3 MHz Speed

From $9.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-12

Volume Pricing

Qty	Unit Price	Extended
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.75	$1,375.00
500	$11.4	$5,700.00
1,000	$9.95	$9,950.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

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EPM5032DC-15 Maximum Ratings & Electrical Characteristics

Family	MAX 5000
Device Type	UV-erasable EPLD (PAL-type CMOS)
Usable Gates	600
Macrocells	32
Propagation Delay (tPD)	15 ns
Maximum Toggle Frequency (fMAX)	83.3 MHz
Supply Voltage (VCC)	5 V (nominal)
Logic Family	CMOS, TTL-compatible I/O
Programmable Pins	16 bidirectional I/O + 4 dedicated input = 20
Total Package Pins	28
Package	CERDIP-28 (windowed, through-hole)
Mounting Type	Through-Hole (DIP)
Operating Temperature	0C to +70C (commercial)
Erasure Method	UV light through ceramic quartz window
Process Technology	CMOS
Lead-Free	unknown

EPM5032DC-15 Pin Configuration

Pin 1	I/O0 — Bidirectional I/O pin, macrocell 0
Pin 2	I/O1 — Bidirectional I/O pin, macrocell 1
Pin 3	I/O2 — Bidirectional I/O pin, macrocell 2
Pin 4	I/O3 — Bidirectional I/O pin, macrocell 3
Pin 5	I/O4 — Bidirectional I/O pin, macrocell 4
Pin 6	I/O5 — Bidirectional I/O pin, macrocell 5
Pin 7	I/O6 — Bidirectional I/O pin, macrocell 6
Pin 8	I/O7 — Bidirectional I/O pin, macrocell 7
Pin 9	IN0 — Dedicated input pin 0
Pin 10	IN1 — Dedicated input pin 1
Pin 11	IN2 — Dedicated input pin 2
Pin 12	IN3 — Dedicated input pin 3
Pin 13	I/O8 — Bidirectional I/O pin, macrocell 8
Pin 14	I/O9 — Bidirectional I/O pin, macrocell 9
Pin 15	I/O10 — Bidirectional I/O pin, macrocell 10
Pin 16	I/O11 — Bidirectional I/O pin, macrocell 11
Pin 17	I/O12 — Bidirectional I/O pin, macrocell 12
Pin 18	I/O13 — Bidirectional I/O pin, macrocell 13
Pin 19	I/O14 — Bidirectional I/O pin, macrocell 14
Pin 20	I/O15 — Bidirectional I/O pin, macrocell 15
Pin 21	GND — Ground (0 V)
Pin 22	VCC — +5 V supply
Pin 23	NC — Not connected (reserved per MAX 5000 family)
Pin 24	NC — Not connected (reserved per MAX 5000 family)
Pin 25	NC — Not connected (reserved per MAX 5000 family)
Pin 26	NC — Not connected (reserved per MAX 5000 family)
Pin 27	NC — Not connected (reserved per MAX 5000 family)
Pin 28	NC — Not connected (reserved per MAX 5000 family)

Safe Operating Area (SOA) & Thermal Characteristics

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM5032DC-15 is suitable for 6 applications: Legacy Industrial Control Glue Logic, Address Decoding and Chip-Select Generation, State Machine Replacement Boards, 5 V TTL Bus Interface Adapters, Educational Laboratory Equipment, Sustaining Engineering and Field Repair.

🏭

Legacy Industrial Control Glue Logic

The EPM5032DC-15 is widely used as glue logic on legacy industrial control boards that were designed in the early 1990s around 5 V TTL and 8086/68000 microprocessors. Its 32 macrocells are sufficient to integrate a complete address decoder, chip-select generator, and I/O-mapped peripheral interface into a single ceramic DIP package, replacing roughly 20 to 30 SSI/MSI TTL packages and saving board area. The 15 ns tPD and 83.3 MHz fMAX meet the timing requirements of 8 MHz 8086 and 10 MHz 68000 bus cycles with comfortable margin, and the 5 V CMOS process is directly compatible with 74LS and 74HC logic families on the same board.

Recommended

🖥️

Address Decoding and Chip-Select Generation

The EPM5032DC-15's 32 macrocells and 20 programmable pins are well matched to address-decoding tasks in 16-bit and 32-bit microprocessor systems. A typical decoder design might use four dedicated inputs for the upper address bits and 8-12 macrocells to generate bank-selected chip enables for memory, I/O and peripheral chips. The 15 ns tPD adds only one propagation stage to the address-to-chip-select path, which is usually within the bus-access budget of an 8086, 68000 or V30 system. The 5 V TTL-compatible I/O thresholds let the EPM5032DC-15 sit directly on the address bus without external buffers.

Recommended

EPM5032DC · Altera EPM5016DC-20 · Altera

🔧

State Machine Replacement Boards

For replacing discrete 74LS / 74HC state machines on legacy boards, the EPM5032DC-15 offers 32 macrocells - each capable of registered or combinatorial output - which is enough for 8 to 16-state FSMs with several output decode terms. The PAL-type AND/OR array architecture preserves the deterministic 15 ns tPD that original designers expected from PAL16L8/PAL22V10 parts, making the EPM5032DC-15 a behavioural drop-in for many 22V10 designs that have outgrown their density. Ceramic DIP packaging also matches the original 22V10 socket footprint on most legacy boards.

Recommended

EPM5032DC-20 · Intel PALCE22V10 (Lower-density legacy alternative)

🌐

5 V TTL Bus Interface Adapters

The EPM5032DC-15 works as a 5 V bus-interface adapter between microprocessors and peripherals that have mismatched timing or voltage-level requirements. Its 16 bidirectional I/O pins can be split into two 8-bit ports, each driven by an independent macrocell group, allowing protocol conversion between, for example, an 8-bit 8086 multiplexed bus and a peripheral with separate address and data buses. The 5 V CMOS I/O with TTL-compatible thresholds means no external level shifters are required when interfacing to standard 74LS/74HC peripherals on the same 5 V rail.

Recommended

EPM5032DC · Altera EPM5016DC-17 · Altera

🎓

Educational Laboratory Equipment

Because the EPM5032DC-15 comes in a windowed CERDIP-28 package that can be erased and reprogrammed with a UV eraser, it is a familiar teaching vehicle in university digital-logic and computer-architecture labs. Students can implement custom decoders, simple CPUs and I/O controllers on a UV-erasable part, then erase and reuse the same device in the next lab session. The through-hole DIP-28 form factor is also friendly to solderless breadboards and wire-wrap prototyping boards that are still common in educational settings.

Recommended

EPM5032DC-25 · Altera EPM5016DC-20 · Altera

✈️

Sustaining Engineering and Field Repair

The EPM5032DC-15's main role today is in sustaining engineering and field repair of legacy systems where the original ceramic-DIP UV-erasable part has failed or needs re-programming with a corrected JEDEC map. Because the CERDIP-28 socketed package can be removed, UV-erased, reprogrammed, and re-soldered without a board redesign, the EPM5032DC-15 is the lowest-risk repair option for boards that must keep running in factories, military systems, and aerospace ground equipment. Sourcing from independent distributors and the surplus market is the standard procurement path.

Recommended

EPM5032DC-20 · Intel EPM5032DM · Intel

Recommended Products Summary

EPM5032DC-20 Intel Used in: Legacy Industrial Control Glue Logic, State Machine Replacement Boards, Sustaining Engineering and Field Repair EPM5016DC-15 Altera Used in: Legacy Industrial Control Glue Logic EPM5032DC Altera Used in: Address Decoding and Chip-Select Generation, 5 V TTL Bus Interface Adapters EPM5016DC-20 Altera Used in: Address Decoding and Chip-Select Generation, Educational Laboratory Equipment PALCE22V10 Lower-density legacy alternative Used in: State Machine Replacement Boards EPM5016DC-17 Altera Used in: 5 V TTL Bus Interface Adapters EPM5032DC-25 Altera Used in: Educational Laboratory Equipment EPM5032DM Intel Used in: Sustaining Engineering and Field Repair

What is the EPM5032DC-15?

The EPM5032DC-15 is a 600-gate, 32-macrocell UV-erasable programmable logic device (PLD) from Altera's MAX 5000 family, with a 15 ns propagation delay. It is built on a 5 V CMOS process, packaged in a 28-pin ceramic DIP (CERDIP-28) with a quartz erasure window, and runs at up to 83.3 MHz toggle frequency. The device is pin-compatible with other MAX 5000 family DIP-28 members and replaces banks of discrete TTL/CMOS glue logic.

How many gates and macrocells does the EPM5032DC-15 have?

The EPM5032DC-15 contains 600 usable gates and 32 macrocells, according to the Altera MAX 5000 datasheet family specification. Each macrocell combines a programmable AND/OR array with a configurable flip-flop, supporting both registered and combinatorial logic. This density is sufficient to integrate a typical decoder-plus-state-machine sub-system into a single package, replacing roughly 20-30 standard SSI/MSI TTL packages.

What is the propagation delay and fMAX of the EPM5032DC-15?

The EPM5032DC-15 is specified at a 15 ns pin-to-pin propagation delay (tPD) and a maximum toggle frequency of 83.3 MHz. The 'DC-15' suffix decodes as DIP / commercial grade / 15 ns tPD; the related 'DC-20' is a slower 20 ns part and 'DC-25' is 25 ns. All three share the same CERDIP-28 pinout and macrocell architecture, so the speed grade can be swapped on a populated board if timing margins allow.

How do you erase and reprogram the EPM5032DC-15?

The EPM5032DC-15 is erased by exposing the quartz window on top of the CERDIP-28 package to short-wave UV light, typically a 12,000 uW/cm^2 UV-C source for 20-40 minutes. After erasure, the device is programmed via a standard Altera programming hardware such as the PLP4 or a third-party programmer using a JEDEC fuse map. In-circuit reprogramming is not possible - the part must be removed, erased, and reprogrammed, then reseated.

Is the EPM5032DC-15 still in production?

No - the EPM5032DC-15 is obsolete and not recommended for new designs. Altera (now part of Intel) discontinued the entire MAX 5000 UV-erasable EPLD family in the late 1990s as surface-mount MAX 7000 and later MAX II CPLDs took over the same market segment. Current stock is limited to authorized distributor inventory, independent distributors, and the surplus market; lead times and pricing can vary widely.

Where can I buy the EPM5032DC-15 today?

As of 2026-09-12, the EPM5032DC-15 is available through independent distributors such as Win Source, Veswin, Vyrian, Jotrin, Censtry, Kynix, and Semiconductors-Chips, plus the Octopart marketplace aggregating six distributors. Authorised Altera/Intel stocking is no longer active for this part. Expect minimum-order quantities of 1 piece at higher unit pricing than the original 1990s list price, with lead times of 2-6 weeks depending on supplier stock.

What is the current price of the EPM5032DC-15?

As of 2026-09-12, the EPM5032DC-15 lists at approximately 18.50 USD per piece at qty 1, scaling to about 9.95 USD at qty 1000 on independent distributors. These prices are quote-only and fluctuate with availability - the part is obsolete, so spot-market pricing applies. Larger orders and smaller orders can vary by 30-50% from the listed tier prices, and freight-on-board terms depend on the distributor's warehouse location.

What is the lead time for the EPM5032DC-15?

As of 2026-09-12, independent distributors report EPM5032DC-15 lead times of 2-6 weeks for small quantities (1-100 pieces) and 4-10 weeks for larger volumes. Lead time depends on whether stock is held in US, European or Asian warehouses and whether the order must be fulfilled from a single date-code lot. For long-term sustaining engineering, request a multi-year quote and a last-time-buy arrangement from your franchised distributor before inventory dries up.

What is the best drop-in replacement for the EPM5032DC-15?

The closest same-package drop-in replacement for the EPM5032DC-15 is the EPM5032DC-20, which shares the CERDIP-28 footprint and macrocell architecture but is speed-graded to 20 ns instead of 15 ns. Slower grades can substitute into most designs that do not run at the fMAX edge, and they are often more readily available on the surplus market. For modern designs the EPM3032ATC44-10 or EPM240T100C5N MAX II CPLDs are pin-compatible in function but require a different PCB footprint.

EPM5032DC-15 vs EPM5032DC-20 - which is better for a 5 V TTL bus decoder?

For a 5 V TTL bus decoder running well below the fMAX edge, the EPM5032DC-20 is the better choice: it is functionally identical to the EPM5032DC-15 in the same CERDIP-28 package, but with a 20 ns tPD it is typically more available and 20-30% cheaper on the surplus market. Choose the EPM5032DC-15 only if your design requires the 5 ns timing margin for a high-speed state machine or registered I/O running near the 83.3 MHz fMAX edge.

When should I choose the EPM5032DC-15 over a modern CPLD?

Choose the EPM5032DC-15 only for sustaining-engineering work on existing 5 V through-hole boards, such as legacy industrial controllers, military prototypes, or educational equipment. For new designs, modern MAX II (EPM240) or MAX V CPLDs offer higher density, lower power, in-system programmability via JTAG, and surface-mount packages - but they require a PCB redesign. The EPM5032DC-15 remains the path of least resistance when the original board and socket must be preserved.

Is the EPM5032DC-15 pin-compatible with the EPM5032DC?

Yes - the EPM5032DC-15 is pin-compatible with the base EPM5032DC, sharing the same CERDIP-28 pinout, pin assignments, and macrocell architecture. The only difference is the speed grade: the EPM5032DC base part is graded at a slower tPD (typically 25 ns), while the EPM5032DC-15 is 15 ns. The two parts can be swapped on most boards provided the design's worst-case timing path is slower than the slower part's tPD.

What is the difference between DIP and CERDIP for the EPM5032 family?

DIP and CERDIP are both 28-pin through-hole packages with the same pinout, but CERDIP (ceramic DIP) uses a sealed ceramic body with a quartz window on top so the UV-erasable EPROM cells inside the EPLD can be erased by UV light. Standard plastic DIP has no window and is therefore used only for one-time-programmable (OTP) variants such as the EPM5032DM, not for the EPM5032DC UV-erasable parts. For most legacy boards the two are interchangeable in the socket.

What is the operating temperature range of the EPM5032DC-15?

The EPM5032DC-15 is graded for the commercial temperature range of 0C to +70C, as indicated by the 'C' in the part suffix. For industrial (-40C to +85C) or military (-55C to +125C) grades you would choose the EPM5032DI or EPM5032DM series, which are packaged in different ceramic or plastic DIP variants. The CERDIP-28 package itself is rated for the full military range, but the silicon die is binned separately for each temperature grade.

Where can I download the EPM5032DC-15 datasheet PDF?

The EPM5032DC-15 datasheet is part of the Altera MAX 5000 family datasheet, which is hosted on Alldatasheet at https://www.alldatasheet.com/datasheet-pdf/pdf/122508/ALTERA/EPM5032.html (52 pages). The MAX 5000 datasheet covers the full EPM5008 through EPM5192 family, so the EPM5032DC-15 specifications appear in the device-selection tables and AC-timing sections of that document. Local copies are also mirrored on AiPCBA (34 pages) and FPGAkey distributor pages.

Engineering reference data for EPM5032DC-15 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM5032DC-15 when you need the highest-speed 32-macrocell UV-erasable EPLD in the MAX 5000 family for a 5 V through-hole DIP-28 design - typical cases are legacy industrial controllers, military prototypes, and educational lab boards. Choose the EPM5032DC-20 (20 ns tPD) if your worst-case timing path can tolerate the 5 ns slower grade, since it is usually more available on the surplus market and 20-30% cheaper. Choose the EPM5032DM (OTP ceramic DIP) when the design will never be re-programmed and you want to skip UV erasure. For new designs, modern MAX II (EPM240T100C5N) or MAX V CPLDs are recommended; reserve the EPM5032DC-15 for sustaining engineering on existing 5 V boards where the original footprint and socket must be preserved.

Comparison with Alternatives

Parameter	This Product	EPM5032DC-20	EPM5032DC	EPM5032DM	EPM5016DC-15
Brand	Altera	Altera	Altera	Altera	Altera
Package	CERDIP-28 (windowed, DIP-28)	CERDIP-28 - same	CERDIP-28 - same	CERDIP-28 - same	CERDIP-28 - same
Macrocells	32	32	32	32	16
Usable Gates	600	600	600	600	[DATA_NEEDED]
Propagation Delay (tPD)	15 ns	20 ns	~25 ns	15 ns	15 ns
Maximum Toggle Frequency (fMAX)	83.3 MHz	~62 MHz	~50 MHz	83.3 MHz	83.3 MHz
Supply Voltage (VCC)	5 V	5 V	5 V	5 V	5 V
Erasure Method	UV light (windowed CERDIP)	UV light (windowed CERDIP)	UV light (windowed CERDIP)	OTP (no window)	UV light (windowed CERDIP)
Operating Temperature	0C to +70C (commercial)	0C to +70C (commercial)	0C to +70C (commercial)	0C to +70C (commercial)	0C to +70C (commercial)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

Key Differentiators

Highest speed grade in the EPM5032 CERDIP-28 family (vs EPM5032DC-20)
UV-erasable windowed package, not OTP (vs EPM5032DM)
32 macrocells for higher logic density (vs EPM5016DC-15)

Design Notes

Estimated: the EPM5032DC-15 draws approximately 100-150 mA from a 5 V supply, with the ICC value scaling linearly with the system clock frequency and the number of simultaneously switching outputs. Decouple VCC (pin 22) with a 0.1 uF ceramic capacitor placed within 5 mm of the package body and a 10 uF bulk tantalum or aluminum electrolytic capacitor near the DIP-28 socket. The I/O switching current spikes are the dominant AC noise source; distributing several smaller ceramic caps along the VCC/GND pin pair is more effective than a single large bulk cap for high-frequency decoupling.

Cover the ceramic quartz window with an opaque label after programming - ambient UV light (including strong fluorescent lighting and sunlight through windows) can slowly erase the device over weeks or months, causing silent logic failure. Store programmed parts in opaque tubes or conductive foam. Also, the EPM5032DC-15 is NOT pin-compatible with the larger EPM5064 or EPM5128 parts of the same family: the larger parts use different pin counts (DIP-40 and PLCC-68 respectively). Verify the package pin count matches your socket before substitution.

For through-hole DIP-28 sockets on a 2-layer PCB, route all VCC traces on the top layer near pin 22 and GND traces on the bottom layer near pin 21 in a star or grid pattern, with the 0.1 uF decoupling cap connected by short (<= 5 mm) vias to the GND plane. Keep clock and high-speed output traces short and away from analog or sensitive signal traces. For new designs, migrate to surface-mount MAX II CPLDs (EPM240T100 or EPM570) to free board area; only sustain the EPM5032DC-15 footprint when the original 5 V through-hole board is mandatory.

Compliance Information

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Lead Free

Unknown

Halogen Free

Unknown

Conflict Minerals

Unknown

Compliance information not present in the verified web data. The EPM5032DC-15 is an obsolete 1990s ceramic-DIP part; lead-free and RoHS status depend on the specific date-code and original manufacturing lot. AEC-Q100 is not applicable (commercial-grade part, not automotive-qualified).

Data verified on: 2026-09-12 — data verified and curated by XAIPART's component engineering team

Sources: Manufacturer_Datasheet, Distributor, Distributor, Distributor, Distributor, Distributor, Distributor, Distributor

Related Components & Terms

Altera Intel EPM5032DC-15 EPM5032DC-20 EPM5032DC EPM5032DM EPM5016DC-15 MAX 5000 EPLD UV-erasable PLD PAL-type CMOS macrocell programmable AND/OR array CERDIP-28 DIP-28 TTL CMOS 5V logic address decoder chip-select generator glue logic state machine 8086 bus 68000 bus industrial controller obsolete semiconductor last-time-buy AEC-Q100 (not applicable)