EPM5032DC-20 vs EPM5032JC-20 Comparison
Detailed side-by-side comparison of EPM5032DC-20 by Intel and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5032DC-20
EPM5032DC-20 - 600-Gate, 32-Macrocell MAX 5000 CPLD DIP-20 | Intel
EPM5032DC-20 ObsoleteAltera
EPM5032JC-20
EPM5032JC-20 - 32-Macrocell UV PLD, 20ns, 24 Inputs | Altera
EPM5032JC-20 ObsoleteSpecification Comparison
| Parameter | EPM5032DC-20 | EPM5032JC-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.05 | $9.75 |
| Product Family | MAX 5000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Programmable Technology | UV-Erasable / OTP EPROM | β |
| Usable Gates | 600 | β |
| Macrocells | 32 | 32 |
| Maximum Frequency (fCNT) | 71.4 MHz | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Speed Grade | -20 | β |
| Supply Voltage (VCC) | 5 V | β |
| Package | 20-pin DIP (Windowed Ceramic, 0.3" wide) | 68-pin JLCC (windowed ceramic) |
| Mounting Type | Through-Hole | β |
| Logic Blocks | 4 Logic Array Blocks (LABs) | β |
| I/O Pins | [DATA_NEEDED: I/O pin count for DIP-20 variant] | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | β |
| RoHS Status | Compliant (per IC-Components listing) | β |
| Lead Free | [DATA_NEEDED: confirmed lead-free] | β |
| Manufacturer | Altera (now Intel Programmable Solutions Group) | β |
| Programming Method | Altera MAX+PLUS II / Quartus (legacy support) | β |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Family | β | MAX 5000 |
| Logic Array Blocks (LABs) | β | 1 |
| Product Terms (P-terms) | β | 320 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Clock Frequency | β | 62.5 MHz |
| Setup Time | β | 10 ns |
| I/O Lines | β | 16 (bidirectional) |
| Dedicated Inputs | β | 8 |
| Total Inputs | β | 24 |
| Process Technology | β | CMOS |
| Erase Method | β | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | β | 12 V |
| Architecture | β | PAL-type AND-OR array with PIA interconnect |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 5000) |