EPM5032DC-20 vs EPM5032JC-20 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032DC-20 disebabkan oleh Intel dan EPM5032JC-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5032DC-20 EPM5032JC-20
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Programmable Technology UV-Erasable / OTP EPROM —
Usable Gates 600 —
Macrocells 32 32
Maximum Frequency (fCNT) 71.4 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Supply Voltage (VCC) 5 V —
Kemasan 20-pin DIP (Windowed Ceramic, 0.3" wide) 68-pin JLCC (windowed ceramic)
Jenis Pemasangan Through-Hole —
Logic Blocks 4 Logic Array Blocks (LABs) —
I/O Pins [DATA_NEEDED: I/O pin count for DIP-20 variant] —
Suhu Operasi [DATA_NEEDED: commercial/industrial/military grade] —
Status RoHS Compliant (per IC-Components listing) —
Lead Free [DATA_NEEDED: confirmed lead-free] —
Manufacturer Altera (now Intel Programmable Solutions Group) —
Programming Method Altera MAX+PLUS II / Quartus (legacy support) —
Product Type — UV-erasable Programmable Logic Device (PLD)
Family — MAX 5000
Logic Array Blocks (LABs) — 1
Product Terms (P-terms) — 320
Propagation Delay (tPD) — 20 ns
Frekuensi Klock Maksimum — 62.5 MHz
Setup Time — 10 ns
I/O Lines — 16 (bidirectional)
Dedicated Inputs — 8
Total Inputs — 24
Process Technology — CMOS
Erase Method — UV (12V VPP + ultraviolet exposure)
Programming Voltage (VPP) — 12 V
Architecture — PAL-type AND-OR array with PIA interconnect
Status Lingkungan Hidup — Obsolete (legacy Altera MAX 5000)

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