EPM5032DC20 vs EPM5032DC Comparison
Detailed side-by-side comparison of EPM5032DC20 by Altera and EPM5032DC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DC20 | EPM5032DC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $10.40 |
| Device Family | MAX 5000 | β |
| Product Type | UV-erasable PLD (CPLD class) | β |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | β |
| Propagation Delay (tPD) | 20 ns | β |
| Maximum Frequency (Fmax) | 71.4 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Dedicated Inputs | 7 | β |
| I/O Pins | 16 (bidirectional) | β |
| Total Inputs (max) | 24 | β |
| Output Macrocells | 16 | β |
| Clock Inputs | 1 (global) | β |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | β |
| Process Technology | CMOS | β |
| Package | 20-pin Ceramic DIP (DC) with UV window | DIP-24 (ceramic, windowed) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| Mounting Type | Through-Hole (DIP) | Through-hole (DIP) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | β | MAX 5000 |
| Device Type | β | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 1 |
| Speed Grade | β | DC (commercial) |
| Technology | β | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | β | AND array + fixed OR array per macrocell |
| Configuration Memory | β | EPROM (UV-erasable via package window) |
| Pin Count | β | 24 |
| Programming Tool | β | Altera MAX+PLUS II / A+PLUS legacy |
| Lifecycle Status | β | Obsolete (mature legacy) |