EPM5032DC20 vs EPM5032DC Comparación
Comparación detallada lado a lado de EPM5032DC20 por Altera y EPM5032DC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5032DC20 | EPM5032DC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $10,40 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 16 (bidirectional) | — |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | — |
| Encapsulado | 20-pin Ceramic DIP (DC) with UV window | DIP-24 (ceramic, windowed) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| Tipo de montaje | Through-Hole (DIP) | Through-hole (DIP) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 1 |
| Speed Grade | — | DC (commercial) |
| Technology | — | Bipolar EPROM, UV-erasable |
| Programmable Logic Elements | — | AND array + fixed OR array per macrocell |
| Configuration Memory | — | EPROM (UV-erasable via package window) |
| Recuento de pines | — | 24 |
| Programming Tool | — | Altera MAX+PLUS II / A+PLUS legacy |
| Estado del ciclo de vida | — | Obsolete (mature legacy) |