EPM5032DM vs EPM5032DI-25 Comparison

Detailed side-by-side comparison of EPM5032DM by Intel and EPM5032DI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DM EPM5032DI-25
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Device Family MAX 5000 —
Macrocells 32 32
Propagation Delay (tPD) 25 ns 25 ns
Usable Gates 600 to 1000 (typical) —
Logic Inputs 32 —
Process Technology CMOS EEPROM CMOS
Package CDIP-28 (ceramic windowed DIP, 28-pin) Ceramic DIP, windowed (UV-erasable)
Supply Voltage (VCC) 5 V (typical) —
Standby Current [DATA_NEEDED: ICC standby current] —
Operating Temperature -55C to +125C (military/extended, ceramic package) 0C to +70C (commercial)
Programming Technology UV-erasable (windowed) EEPROM —
Logic Function Combinational and registered (synchronous) —
Output Polarity Programmable —
Program Retention Non-volatile (EEPROM) —
Mounting Type Through-hole (DIP) —
RoHS Status Non-compliant (ceramic DIP with UV window) [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Lead-Free No (ceramic DIP contains lead) —
Family — MAX 5000
Device Type — UV-erasable Programmable Logic Device (PLD)
Architecture — PAL-type, CMOS, AND-OR sum-of-products
Product Terms — 320
Logic Gates — [DATA_NEEDED: equivalent gate count]
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Maximum Clock Frequency (fMAX) — 62.5 MHz
Supply Voltage — 5 V
Pin Count — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Development Tool — MAX+PLUS II / A+PLUS
Lifecycle — Not Recommended for New Designs (NRND)

Datasheets & Resources

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