EPM5032DM vs EPM5032DI-25 比較
詳細並排比較 EPM5032DM 由 Intel 與 EPM5032DI-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DM | EPM5032DI-25 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Usable Gates | 600 to 1000 (typical) | — |
| Logic Inputs | 32 | — |
| Process Technology | CMOS EEPROM | CMOS |
| 封裝 | CDIP-28 (ceramic windowed DIP, 28-pin) | Ceramic DIP, windowed (UV-erasable) |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Standby Current | [DATA_NEEDED: ICC standby current] | — |
| 工作溫度 | -55C to +125C (military/extended, ceramic package) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable (windowed) EEPROM | — |
| Logic Function | Combinational and registered (synchronous) | — |
| Output Polarity | Programmable | — |
| Program Retention | Non-volatile (EEPROM) | — |
| 安裝類型 | Through-hole (DIP) | — |
| RoHS 狀態 | Non-compliant (ceramic DIP with UV window) | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Lead-Free | No (ceramic DIP contains lead) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-erasable Programmable Logic Device (PLD) |
| Architecture | — | PAL-type, CMOS, AND-OR sum-of-products |
| Product Terms | — | 320 |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 供應電壓 | — | 5 V |
| 腳位數 | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |