EPM5032DM vs EPM5032DI-25 比較
詳細な並列比較: EPM5032DM メーカー: Intel および EPM5032DI-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DM | EPM5032DI-25 |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $15.90 | $18.20 |
| Device Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Usable Gates | 600 to 1000 (typical) | — |
| Logic Inputs | 32 | — |
| Process Technology | CMOS EEPROM | CMOS |
| パッケージ | CDIP-28 (ceramic windowed DIP, 28-pin) | Ceramic DIP, windowed (UV-erasable) |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Standby Current | [DATA_NEEDED: ICC standby current] | — |
| 動作温度 | -55C to +125C (military/extended, ceramic package) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable (windowed) EEPROM | — |
| Logic Function | Combinational and registered (synchronous) | — |
| Output Polarity | Programmable | — |
| Program Retention | Non-volatile (EEPROM) | — |
| 実装タイプ | Through-hole (DIP) | — |
| RoHS ステータス | Non-compliant (ceramic DIP with UV window) | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Lead-Free | No (ceramic DIP contains lead) | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-erasable Programmable Logic Device (PLD) |
| Architecture | — | PAL-type, CMOS, AND-OR sum-of-products |
| Product Terms | — | 320 |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 電源電圧 | — | 5 V |
| ピン数 | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Development Tool | — | MAX+PLUS II / A+PLUS |
| Lifecycle | — | Not Recommended for New Designs (NRND) |