EPM5032JC-20 vs EPM5032DC-25 Comparison

Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032DC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032JC-20 EPM5032DC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Product Type UV-erasable Programmable Logic Device (PLD) —
Family MAX 5000 —
Macrocells 32 32
Logic Array Blocks (LABs) 1 —
Product Terms (P-terms) 320 —
Propagation Delay (tPD) 20 ns —
Maximum Clock Frequency 62.5 MHz —
Setup Time 10 ns —
I/O Lines 16 (bidirectional) —
Dedicated Inputs 8 —
Total Inputs 24 —
Package 68-pin JLCC (windowed ceramic) CDIP-28 (Windowed Ceramic DIP-28)
Process Technology CMOS CMOS, EPROM (UV-Erasable)
Erase Method UV (12V VPP + ultraviolet exposure) —
Programming Voltage (VPP) 12 V —
Architecture PAL-type AND-OR array with PIA interconnect PAL-Type, Single-LAB, 32-Macrocell
Lifecycle Status Obsolete (legacy Altera MAX 5000) —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Operating Temperature — [DATA_NEEDED: operating temperature range]
RoHS Status — Lead Free / RoHS Compliant (per distributor listings)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

Datasheets & Resources

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