EPM5032JC-20 vs EPM5032DC-25 比較
詳細な並列比較: EPM5032JC-20 メーカー: Altera および EPM5032DC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032JC-20 | EPM5032DC-25 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $3.55 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 最大クロック周波数 | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | — |
| Total Inputs | 24 | — |
| パッケージ | 68-pin JLCC (windowed ceramic) | CDIP-28 (Windowed Ceramic DIP-28) |
| Process Technology | CMOS | CMOS, EPROM (UV-Erasable) |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-Type, Single-LAB, 32-Macrocell |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 5000) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |
| RoHS ステータス | — | Lead Free / RoHS Compliant (per distributor listings) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |