EPM5032JC vs EPM5032JC-20 Comparison
Detailed side-by-side comparison of EPM5032JC by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5032JC-20
EPM5032JC-20 - 32-Macrocell UV PLD, 20ns, 24 Inputs | Altera
EPM5032JC-20 ObsoleteSpecification Comparison
| Parameter | EPM5032JC | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.50 | $9.75 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | β |
| Maximum I/O Pins | 40 | β |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | 20 ns |
| Supply Voltage (VCC) | 5 V | β |
| Input Type | TTL-compatible | β |
| Output Type | TTL/CMOS-compatible | β |
| Package | PLCC-44 | 68-pin JLCC (windowed ceramic) |
| Operating Temperature | 0C to +70C (commercial) | β |
| Mounting Type | Surface Mount (J-lead) | β |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | β |
| Design Software | MAX+PLUS II / Quartus legacy | β |
| JEDEC Standard | JEDEC PLCC-44 footprint | β |
| RoHS Status | unknown | β |
| Lead-Free | unknown | β |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | β | 1 |
| Product Terms (P-terms) | β | 320 |
| Maximum Clock Frequency | β | 62.5 MHz |
| Setup Time | β | 10 ns |
| I/O Lines | β | 16 (bidirectional) |
| Dedicated Inputs | β | 8 |
| Total Inputs | β | 24 |
| Process Technology | β | CMOS |
| Erase Method | β | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | β | 12 V |
| Architecture | β | PAL-type AND-OR array with PIA interconnect |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 5000) |