EPM5032JC vs EPM5032JC-20 对比
详细并排对比 EPM5032JC 出自 Altera 和 EPM5032JC-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032JC | EPM5032JC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.50 | $9.75 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | 20 ns |
| Supply Voltage (VCC) | 5 V | — |
| Input Type | TTL-compatible | — |
| 输出类型 | TTL/CMOS-compatible | — |
| 封装 | PLCC-44 | 68-pin JLCC (windowed ceramic) |
| 工作温度 | 0C to +70C (commercial) | — |
| 安装类型 | Surface Mount (J-lead) | — |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| RoHS 状态 | unknown | — |
| Lead-Free | unknown | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| 最大时钟频率 | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Dedicated Inputs | — | 8 |
| Total Inputs | — | 24 |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| Architecture | — | PAL-type AND-OR array with PIA interconnect |
| 生命周期状态 | — | Obsolete (legacy Altera MAX 5000) |