EPM5032LC-25 vs EPM5032JC Comparison
Detailed side-by-side comparison of EPM5032LC-25 by Altera and EPM5032JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-25 | EPM5032JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $13.50 |
| Device Family | MAX 5000 | β |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | β |
| Technology | CMOS, UV-erasable / OTP | β |
| Macrocells | 32 | 32 |
| Product Terms | 320 | β |
| Dedicated Inputs | 7 | β |
| I/O Pins | 16 bidirectional | β |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | β |
| Propagation Delay (tPD) | 25 ns | [DATA_NEEDED: specific speed grade value] |
| Maximum Internal Frequency | 62.5 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% (4.5 V to 5.5 V) | 5 V |
| I/O Standard | 5 V CMOS | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial, "LC" suffix) | 0C to +70C (commercial) |
| Package | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | PLCC-44 |
| Mounting Type | Surface Mount, socket-compatible | Surface Mount (J-lead) |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | β |
| RoHS Status | Not RoHS compliant (legacy Altera product) | unknown |
| Family | β | MAX 5000 EPLD |
| Logic Gates | β | 600 usable gates |
| Maximum I/O Pins | β | 40 |
| Input Type | β | TTL-compatible |
| Output Type | β | TTL/CMOS-compatible |
| Programmability | β | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | β | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | β | JEDEC PLCC-44 footprint |
| Lead-Free | β | unknown |