EPM5032LC-25 vs EPM5032JC 비교
다음의 상세 나란히 비교: EPM5032LC-25 제조: Altera 및 EPM5032JC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5032LC-25 | EPM5032JC |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $8.20 | $13.50 |
| Device Family | MAX 5000 | — |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Dedicated Inputs | 7 | — |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | — |
| Propagation Delay (tPD) | 25 ns | [DATA_NEEDED: specific speed grade value] |
| Maximum Internal Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% (4.5 V to 5.5 V) | 5 V |
| I/O Standard | 5 V CMOS | — |
| 동작 온도 | 0 °C to +70 °C (commercial, "LC" suffix) | 0C to +70C (commercial) |
| 패키지 | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | PLCC-44 |
| 실장 유형 | Surface Mount, socket-compatible | Surface Mount (J-lead) |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | — |
| RoHS 상태 | Not RoHS compliant (legacy Altera product) | unknown |
| Family | — | MAX 5000 EPLD |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Input Type | — | TTL-compatible |
| 출력 유형 | — | TTL/CMOS-compatible |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Lead-Free | — | unknown |