EPM5064JC-2 vs EPM5064JC-1 Comparison

Detailed side-by-side comparison of EPM5064JC-2 by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC-2 EPM5064JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 5000 MAX 5000
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
Propagation Delay (tPD) 45 ns —
Maximum Clock Frequency (fMAX) 50 MHz —
Usable Gates 1250 1250 (typical)
Dedicated Inputs 7 [DATA_NEEDED: dedicated input count]
I/O Pins 28 —
Interconnect Programmable Interconnect Array (PIA) —
Technology CMOS, UV-erasable EPROM —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V nominal (4.75 V – 5.25 V)
Programming Method UV-erase + EPROM programmer (not ISP) Altera Logic Programmer + MasterBlaster/ByteBlasterMV
Package 28-pin CLCC (J-lead, ceramic, windowed) 44-pin PLCC (J-lead, windowed ceramic)
Operating Temperature [DATA_NEEDED: commercial or industrial grade] 0 °C to +70 °C (commercial, -JC suffix)
Compliance RoHS status unknown (ceramic/J-lead windowed part, legacy product) —
Device Type — EPLD (Erasable Programmable Logic Device)
Macro Cells — 64
Logic Elements — 128 (Logic Array Blocks)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Process Technology — 0.8 µm CMOS
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
Mounting Type — Surface Mount (PLCC socket recommended)
Erasure Method — UV-erasable through quartz window
JTAG Boundary Scan — Not supported (classic MAX architecture)
RoHS Status — Non-compliant (windowed ceramic, contains Pb in glass frit)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

Datasheets & Resources

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