EPM5064JC-2 vs EPM5064JC-1 比較
詳細並排比較 EPM5064JC-2 由 Altera 與 EPM5064JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC-2 | EPM5064JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Usable Gates | 1250 | 1250 (typical) |
| Dedicated Inputs | 7 | [DATA_NEEDED: dedicated input count] |
| I/O Pins | 28 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V nominal (4.75 V – 5.25 V) |
| Programming Method | UV-erase + EPROM programmer (not ISP) | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| 封裝 | 28-pin CLCC (J-lead, ceramic, windowed) | 44-pin PLCC (J-lead, windowed ceramic) |
| 工作溫度 | [DATA_NEEDED: commercial or industrial grade] | 0 °C to +70 °C (commercial, -JC suffix) |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Process Technology | — | 0.8 µm CMOS |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| 安裝類型 | — | Surface Mount (PLCC socket recommended) |
| Erasure Method | — | UV-erasable through quartz window |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| RoHS 狀態 | — | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |