EPM5064JC vs EPM5032JC Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5032JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5032JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $13.50 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable PLD) | β |
| Macrocells | 64 | 32 |
| Usable Gates | 1,250 (approx.) | β |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | PLCC-44 |
| Mounting Type | Surface Mount (socketed) | Surface Mount (J-lead) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | unknown |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Logic Gates | β | 600 usable gates |
| Maximum I/O Pins | β | 40 |
| Propagation Delay (tPD) | β | [DATA_NEEDED: specific speed grade value] |
| Input Type | β | TTL-compatible |
| Output Type | β | TTL/CMOS-compatible |
| Programmability | β | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | β | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | β | JEDEC PLCC-44 footprint |