EPM5064JC vs EPM5032JC 比較
詳細並排比較 EPM5064JC 由 Altera 與 EPM5032JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC | EPM5032JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 32 |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| 封裝 | 68-pin PLCC (JEDEC) | PLCC-44 |
| 安裝類型 | Surface Mount (socketed) | Surface Mount (J-lead) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | unknown |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: specific speed grade value] |
| Input Type | — | TTL-compatible |
| 輸出類型 | — | TTL/CMOS-compatible |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |