EPM5064JC - 64-Macrocell MAX 5000 EPLD, 68-Pin PLCC | Altera
MPN: EPM5064JC β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.1 | $7,100.00 |
Drop-in alternatives for EPM5064JC β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5032JC
β Drop-Inβ In Stock
$13.5 / Unit
View Datasheet βEPM5032JC-20
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM5032JC25
β Drop-Inβ In Stock
$23.95 / Unit
View Datasheet βEPM5128JC
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM5064JC-1
β Drop-Inβ In Stock
$18.25 / Unit
View Datasheet βEPM5064JC Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | EPLD (Erasable PLD) |
| Macrocells | 64 |
| Usable Gates | 1,250 (approx.) |
| Logic Array Inputs | 36 |
| Logic Array Outputs | 64 |
| Package | 68-pin PLCC (JEDEC) |
| Mounting Type | Surface Mount (socketed) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) |
| I/O Logic Level | TTL / CMOS compatible |
| Configuration Memory | EPROM (UV-erasable window or OTP) |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) |
EPM5064JC Pin Configuration
| Pin 1 | I/O β General-purpose I/O pin |
| Pin 2 | I/O β General-purpose I/O pin |
| Pin 3 | I/O β General-purpose I/O pin |
| Pin 4 | I/O β General-purpose I/O pin |
| Pin 5 | I/O β General-purpose I/O pin |
| Pin 6 | I/O β General-purpose I/O pin |
| Pin 7 | I/O β General-purpose I/O pin |
| Pin 8 | I/O β General-purpose I/O pin |
| Pin 9 | I/O β General-purpose I/O pin |
| Pin 10 | I/O β General-purpose I/O pin |
| Pin 11 | I/O β General-purpose I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β General-purpose I/O pin |
| Pin 14 | I/O β General-purpose I/O pin |
| Pin 15 | I/O β General-purpose I/O pin |
| Pin 16 | I/O β General-purpose I/O pin |
| Pin 17 | I/O β General-purpose I/O pin |
| Pin 18 | I/O β General-purpose I/O pin |
| Pin 19 | I/O β General-purpose I/O pin |
| Pin 20 | I/O β General-purpose I/O pin |
| Pin 21 | I/O β General-purpose I/O pin |
| Pin 22 | I/O β General-purpose I/O pin |
| Pin 23 | I/O β General-purpose I/O pin |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β General-purpose I/O pin |
| Pin 26 | I/O β General-purpose I/O pin |
| Pin 27 | I/O β General-purpose I/O pin |
| Pin 28 | I/O β General-purpose I/O pin |
| Pin 29 | I/O β General-purpose I/O pin |
| Pin 30 | I/O β General-purpose I/O pin |
| Pin 31 | I/O β General-purpose I/O pin |
| Pin 32 | I/O β General-purpose I/O pin |
| Pin 33 | I/O β General-purpose I/O pin |
| Pin 34 | I/O β General-purpose I/O pin |
| Pin 35 | I/O β General-purpose I/O pin |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β General-purpose I/O pin |
| Pin 38 | I/O β General-purpose I/O pin |
| Pin 39 | I/O β General-purpose I/O pin |
| Pin 40 | I/O β General-purpose I/O pin |
| Pin 41 | I/O β General-purpose I/O pin |
| Pin 42 | I/O β General-purpose I/O pin |
| Pin 43 | I/O β General-purpose I/O pin |
| Pin 44 | I/O β General-purpose I/O pin |
| Pin 45 | I/O β General-purpose I/O pin |
| Pin 46 | I/O β General-purpose I/O pin |
| Pin 47 | I/O β General-purpose I/O pin |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β General-purpose I/O pin |
| Pin 50 | I/O β General-purpose I/O pin |
| Pin 51 | I/O β General-purpose I/O pin |
| Pin 52 | I/O β General-purpose I/O pin |
| Pin 53 | I/O β General-purpose I/O pin |
| Pin 54 | I/O β General-purpose I/O pin |
| Pin 55 | I/O β General-purpose I/O pin |
| Pin 56 | I/O β General-purpose I/O pin |
| Pin 57 | I/O β General-purpose I/O pin |
| Pin 58 | I/O β General-purpose I/O pin |
| Pin 59 | I/O β General-purpose I/O pin |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β General-purpose I/O pin |
| Pin 62 | I/O β General-purpose I/O pin |
| Pin 63 | I/O β General-purpose I/O pin |
| Pin 64 | I/O β General-purpose I/O pin |
| Pin 65 | I/O β General-purpose I/O pin |
| Pin 66 | I/O β General-purpose I/O pin |
| Pin 67 | I/O β General-purpose I/O pin |
| Pin 68 | VCC β +5V power supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5064JC is suitable for 6 applications: Legacy 5V Glue Logic and Address Decoding, Bus Interface Bridging (8-bit to 16-bit / 16-bit to 32-bit), State-Machine Controllers in Industrial Instrumentation, Replacement of Discrete 74LS / 74HC Logic (Board Consolidation), Aerospace and Defense Legacy System Sustainment, Wait-State Generation and Bus Arbitration Logic.
Legacy 5V Glue Logic and Address Decoding
The EPM5064JC's 64 macrocells and 36 input / 64 output Logic Array make it well suited for legacy 5V glue-logic tasks such as memory address decoding, chip-select generation, and wait-state insertion. The MAX 5000 deterministic pin-to-pin delay (tPD) eliminates the variable routing delays that plague early FPGAs, simplifying static timing closure in systems where multiple peripheral devices must be selected within a fixed clock cycle. The 5V CMOS/TTL-compatible I/O interfaces directly to 74LS/74HC logic and 5V microprocessors without level shifters, preserving signal integrity in industrial and aerospace systems designed before the 3.3V transition. The 68-pin PLCC socketed package supports field-replaceable units, which is critical for long-lifecycle industrial control systems where downtime is costly.
Recommended
Bus Interface Bridging (8-bit to 16-bit / 16-bit to 32-bit)
The EPM5064JC is widely deployed as a bus-interface bridge between microprocessors and peripherals of differing bus widths, where its 64 macrocells can implement the multiplexers, latches, and control signal generators required for transparent bus translation. With 64 outputs and 36 inputs, the device can simultaneously buffer address and data lines while generating direction-control signals for bidirectional buffers, all within a single chip. The deterministic MAX 5000 interconnect avoids the bus-skew issues common with discrete 74LS245 / 74LS244 implementations, improving setup/hold margins at higher clock rates. The 5V tolerance allows direct connection to legacy ISA, VME, and PC/104 bus architectures still used in industrial and military systems as of 2026.
Recommended
State-Machine Controllers in Industrial Instrumentation
The EPM5064JC's registered macrocell architecture and predictable timing are well matched to state-machine-based controllers used in industrial instrumentation, motor drives, and process-control equipment. Each macrocell contains a flip-flop and a programmable I/O architecture, allowing the device to implement Moore or Mealy state machines with up to 64 output states using a single chip, reducing board area compared with discrete 74LS/74HC PAL/GAL implementations. The EPROM-based configuration retains the state machine definition without external boot memory, eliminating the inrush and brownout failure modes of SRAM-based FPGAs in electrically noisy industrial environments. The 68-pin PLCC package is rated for the operating temperature grades required by industrial control cabinets and outdoor instrumentation enclosures.
Recommended
Replacement of Discrete 74LS / 74HC Logic (Board Consolidation)
A common application for the EPM5064JC is the consolidation of multiple discrete 74LS / 74HC SSI/MSI logic packages into a single programmable device, reducing PCB area, component count, and assembly cost in legacy designs. The 64 macrocells can replace 10-20 standard logic packages depending on the logic density of the original implementation, while preserving the 5V logic levels and TTL-compatible I/O of the original discrete solution. The MAX 5000 deterministic timing model also improves over discrete logic by eliminating the cumulative propagation delay of cascaded gates, which is critical in timing-sensitive applications such as memory control and DMA arbitration. Engineers can use MAX+PLUS II to capture schematics or HDL and re-target the design across the MAX 5000 family (EPM5032 to EPM5192) without PCB changes, supporting design reuse across product variants.
Recommended
Aerospace and Defense Legacy System Sustainment
The EPM5064JC remains in active use in aerospace and defense programs where long qualification cycles and stringent change-control requirements make PCB redesigns prohibitively expensive, and where the part's mature datasheet and established reliability database provide the documentation needed for continued airworthiness certification. The EPROM-based configuration is non-volatile and immune to radiation-induced bit flips that affect SRAM-based FPGAs, a key advantage in space and high-altitude applications. The 68-pin PLCC package supports socketed replacement for line-replaceable units (LRUs), enabling field serviceability without soldering. As of 2026-09-12, defense sustainment contracts continue to source the EPM5064JC through authorized aftermarket channels despite its obsolete commercial lifecycle status.
Recommended
Wait-State Generation and Bus Arbitration Logic
The EPM5064JC is well suited for wait-state generation and bus arbitration in legacy microprocessor systems, where the deterministic MAX 5000 timing model simplifies the timing analysis required to insert the correct number of wait states for slow peripherals. The 64 macrocells can implement a multi-master arbiter with priority encoding, grant signal generation, and bus-request latching in a single device, replacing 4-6 discrete 74LS/74HC packages. The 5V CMOS/TTL I/O interfaces directly to 8086, 68000, and similar legacy processors without external transceivers. The 68-pin PLCC package is socket-compatible with the EPM5032 and EPM5128, allowing board-level density scaling based on the actual arbitration logic complexity.
Recommended
Recommended Products Summary
Engineering reference data for EPM5064JC β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5032JC | EPM5032JC-20 | EPM5032JC25 | EPM5128JC | EPM5064JC-1 |
|---|---|---|---|---|---|---|
| Package | PLCC-68 | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) | PLCC-68 (same) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 64 | 32 (-50%) | 32 (-50%) | 32 (-50%) | 128 (+100%) | 64 (same) |
| Usable Gates (approx.) | 1,250 | 600 (-52%) | 600 (-52%) | 600 (-52%) | 2,500 (+100%) | 1,250 (same) |
| Family | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Speed Grade | [DATA_NEEDED: tPD grade] | [DATA_NEEDED] | tPD 20 ns | tPD 25 ns | [DATA_NEEDED] | tPD grade -1 |
| Configuration Memory | EPROM (UV/OTP) | EPROM (UV/OTP) | EPROM (UV/OTP) | EPROM (UV/OTP) | EPROM (UV/OTP) | EPROM (UV/OTP) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Mid-density MAX 5000 EPLD with 64 macrocells (vs EPM5032JC)
- 100% pin-compatible with EPM5128JC for upward migration (vs EPM5128JC)
- Non-volatile EPROM configuration eliminates boot memory (vs EPM240T100C5N (MAX II CPLD))
Design Notes
The EPM5064JC operates from a single 5V supply (4.75V to 5.25V) with multiple VCC/GND pins distributed across the 68-pin PLCC package. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package, and add a single 10 uF bulk tantalum or aluminum electrolytic capacitor near the device to handle switching transients from simultaneous I/O transitions. The EPROM-based configuration draws negligible standby current, but dynamic I/O switching can produce brief current spikes β adequate bulk decoupling prevents these from coupling into adjacent analog or memory circuits.
When laying out a PCB for the EPM5064JC in a 68-pin PLCC socket, allocate a 1.27 mm-pitch land pattern with a center socket footprint compatible with standard PLCC sockets (JEDEC MO-047). Keep input and output traces short and matched within the same Logic Array Block (LAB) group to minimize interconnect-induced delay skew. Because the MAX 5000 architecture uses a deterministic interconnect model, designers can rely on datasheet tPD values without statistical derating, simplifying timing closure. For mixed 5V/3.3V designs, add external level-shifters on all I/O lines crossing the voltage domains β the EPM5064JC lacks 3.3V tolerance.
Estimated: programming the EPM5064JC requires Altera's legacy MAX+PLUS II toolchain or Quartus II with legacy device support; modern Quartus Prime releases may not include MAX 5000 device support, so engineers should verify tool compatibility before committing to the part for a new design. Additionally, the EPROM configuration memory requires a UV-erasable windowed package for re-programming β OTP (one-time-programmable) variants cannot be re-used after the initial programming, which has implications for prototype vs production builds. The part's 5V-only I/O is incompatible with 3.3V logic without external level shifters; verify all connected devices share the 5V supply domain.
Compliance Information
Compliance status marked unknown because the original Altera datasheet predates RoHS/REACH directives and limited public disclosure is available from current distributors as of 2026-09-12. For RoHS-critical designs, request a manufacturer compliance letter from your distributor or migrate to the MAX II / MAX V family, which is fully RoHS compliant.
