EPM5064JC vs EPM5064LC-1 Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5064LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5064LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $9.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | β |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | 1.25K (approx.) |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | 44-pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount (socketed) | β |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.75 V to 5.25 V |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature range] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 4 |
| Internal Operating Frequency | β | 62.5 MHz |
| Propagation Delay (tPD) | β | 40 ns |
| Input Lines | β | 36 |
| Dedicated Inputs | β | 7 |
| Output Lines | β | 28 |
| Programming Technology | β | OTP / UV-Erasable EPROM |
| Process Technology | β | CMOS |
| Programming Interface | β | JTAG (ByteBlaster-compatible) |