EPM5064JC1 vs EPM5064JC-1 Comparison
Detailed side-by-side comparison of EPM5064JC1 by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC1 | EPM5064JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1.05 | $18.25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD / EPLD (Erasable PLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 64 | β |
| Logic Array Blocks (LABs) | 4 | β |
| Usable Gates | 1.25K | 1250 (typical) |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | β |
| External Clock Input (max) | 50 MHz | β |
| I/O Pins | 28 | β |
| Dedicated Inputs | 7 | [DATA_NEEDED: dedicated input count] |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | β |
| Operating Voltage (VCC) | 5 V | β |
| Program Type | EPROM (one-time programmable, UV-erasable) | β |
| Process Technology | CMOS | 0.8 Β΅m CMOS |
| Package | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-lead, windowed ceramic) |
| Operating Temperature (JC suffix) | 0Β°C to +70Β°C (commercial) | β |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | β |
| RoHS Status | unknown | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free Status | unknown | β |
| Macro Cells | β | 64 |
| Logic Elements | β | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | β | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | β | [DATA_NEEDED: tPD typical/max in ns] |
| Supply Voltage (VCC) | β | 5 V nominal (4.75 V β 5.25 V) |
| Programmable Pins | β | 36 (typical I/O, 44-pin PLCC) |
| Mounting Type | β | Surface Mount (PLCC socket recommended) |
| Operating Temperature | β | 0 Β°C to +70 Β°C (commercial, -JC suffix) |
| Erasure Method | β | UV-erasable through quartz window |
| Programming Method | β | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | β | Not supported (classic MAX architecture) |
| Military/Avionics SMD | β | 5962-01-417-3750 (QML variant: EPM5064JM/883) |