EPM5064JC1 vs EPM5064JC-1 比較
詳細な並列比較: EPM5064JC1 メーカー: Altera および EPM5064JC-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5064JC1 | EPM5064JC-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.05 | $18.25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD / EPLD (Erasable PLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1.25K | 1250 (typical) |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | — |
| External Clock Input (max) | 50 MHz | — |
| I/O Pins | 28 | — |
| Dedicated Inputs | 7 | [DATA_NEEDED: dedicated input count] |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | — |
| Operating Voltage (VCC) | 5 V | — |
| Program Type | EPROM (one-time programmable, UV-erasable) | — |
| Process Technology | CMOS | 0.8 µm CMOS |
| パッケージ | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-lead, windowed ceramic) |
| Operating Temperature (JC suffix) | 0°C to +70°C (commercial) | — |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | — |
| RoHS ステータス | unknown | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free Status | unknown | — |
| Macro Cells | — | 64 |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Supply Voltage (VCC) | — | 5 V nominal (4.75 V – 5.25 V) |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| 実装タイプ | — | Surface Mount (PLCC socket recommended) |
| 動作温度 | — | 0 °C to +70 °C (commercial, -JC suffix) |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |