EPM5064LC vs EPM5064JC-1 Comparison

Detailed side-by-side comparison of EPM5064LC by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064LC EPM5064JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Programming Type OTP (One-Time-Programmable, UV-erasable EPROM) —
Macro Cells 64 64
Usable Gates 1.25K 1250 (typical)
Logic Array Blocks (LABs) 4 —
Propagation Delay (tPD) 55 ns —
Total Inputs 36 (7 dedicated + 29 I/O) —
I/O Pins 28 bidirectional + 4 dedicated input —
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V nominal (4.75 V – 5.25 V)
Operating Temperature 0C to +70C (Commercial) 0 °C to +70 °C (commercial, -JC suffix)
Package PLCC-44 (LCC-44, J-lead) 44-pin PLCC (J-lead, windowed ceramic)
Process Technology CMOS EPROM 0.8 µm CMOS
Mounting Type Surface Mount Surface Mount (PLCC socket recommended)
RoHS Status [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] Non-compliant (windowed ceramic, contains Pb in glass frit)
Lead Free [DATA_NEEDED: lead-free status] —
Logic Elements — 128 (Logic Array Blocks)
Maximum Operating Frequency — 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD typical/max in ns]
Programmable Pins — 36 (typical I/O, 44-pin PLCC)
Dedicated Inputs — [DATA_NEEDED: dedicated input count]
Erasure Method — UV-erasable through quartz window
Programming Method — Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan — Not supported (classic MAX architecture)
Military/Avionics SMD — 5962-01-417-3750 (QML variant: EPM5064JM/883)

Datasheets & Resources

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