EPM5064LC vs EPM5064JC-1 Comparaison
Comparaison détaillée côte à côte de EPM5064LC par Altera et EPM5064JC-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5064LC | EPM5064JC-1 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $18,25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Programming Type | OTP (One-Time-Programmable, UV-erasable EPROM) | — |
| Macro Cells | 64 | 64 |
| Usable Gates | 1.25K | 1250 (typical) |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Total Inputs | 36 (7 dedicated + 29 I/O) | — |
| I/O Pins | 28 bidirectional + 4 dedicated input | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal (4.75 V – 5.25 V) |
| Température de fonctionnement | 0C to +70C (Commercial) | 0 °C to +70 °C (commercial, -JC suffix) |
| Boîtier | PLCC-44 (LCC-44, J-lead) | 44-pin PLCC (J-lead, windowed ceramic) |
| Process Technology | CMOS EPROM | 0.8 µm CMOS |
| Type de montage | Surface Mount | Surface Mount (PLCC socket recommended) |
| Statut RoHS | [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD typical/max in ns] |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| Dedicated Inputs | — | [DATA_NEEDED: dedicated input count] |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |