EPM5128GC-2 vs EPM5128JC-1 Comparison
Detailed side-by-side comparison of EPM5128GC-2 by Altera and EPM5128JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128GC-2 | EPM5128JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Macrocells | 128 | 128 |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 50 MHz | 62.5 MHz |
| Propagation Delay (tPD) | Approx. 25 ns (typical, -2 speed grade) | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | 68-pin PGA (Pin Grid Array) | — |
| Package Code (per Partstack) | WPGA | — |
| Number of Terminals | 68 | — |
| Programming Technology | UV-erasable EPROM | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| Grade (per Partstack) | COMMERCIAL | — |
| Terminal Form | PIN/PEG | — |
| Configuration Memory | Non-volatile, one-time programmable (erasable via UV) | Non-volatile EPROM (UV-erasable) |
| Device Type | — | Erasable Programmable Logic Device (EPLD/CPLD) |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Package | — | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| Mounting Type | — | Surface Mount |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| RoHS Status | — | non_compliant (ceramic windowed package) |
| Lifecycle Status | — | Obsolete - last-time-buy inventory only |