EPM5130GI vs EPM5130LC Comparison
Detailed side-by-side comparison of EPM5130GI by Altera and EPM5130LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130GI | EPM5130LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.20 | $15.60 |
| Device Family | MAX 5000 | β |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| Dedicated Inputs | 19 | 19 |
| Total Inputs | 68 | β |
| I/O Pins | 48 | β |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | β |
| External Clock Pins | 1 | β |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Supply Voltage | 5 V | β |
| Package | Ceramic Pin Grid Array (PGA), windowed | JLCC-68 (J-Lead Ceramic Chip Carrier) |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: commercial/industrial/military grade] |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic JLCC, contains lead) |
| Programming Method | UV erasure + EPROM programming | β |
| Series | β | MAX 5000 |
| Family | β | MAX 5000 (EPM51xx) |
| User I/O Pins | β | 48 |
| Total Inputs (Dedicated + I/O) | β | 68 |
| Maximum Internal Clock Frequency | β | 50 MHz |
| Global Clock Inputs | β | 1 |
| Configuration Technology | β | UV-Erasable / OTP EPROM |
| Supply Voltage (VCC) | β | 4.5 V to 5.5 V |
| I/O Standard | β | TTL-compatible |
| Mounting Type | β | Surface Mount |