EPM5130GI vs EPM5130LC Comparación
Comparación detallada lado a lado de EPM5130GI por Altera y EPM5130LC por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130GI | EPM5130LC |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,20 | $15,60 |
| Device Family | MAX 5000 | — |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Dedicated Inputs | 19 | 19 |
| Total Inputs | 68 | — |
| I/O Pins | 48 | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| External Clock Pins | 1 | — |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Tensión de alimentación | 5 V | — |
| Encapsulado | Ceramic Pin Grid Array (PGA), windowed | JLCC-68 (J-Lead Ceramic Chip Carrier) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic JLCC, contains lead) |
| Programming Method | UV erasure + EPROM programming | — |
| Series | — | MAX 5000 |
| Family | — | MAX 5000 (EPM51xx) |
| User I/O Pins | — | 48 |
| Total Inputs (Dedicated + I/O) | — | 68 |
| Maximum Internal Clock Frequency | — | 50 MHz |
| Global Clock Inputs | — | 1 |
| Configuration Technology | — | UV-Erasable / OTP EPROM |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| I/O Standard | — | TTL-compatible |
| Tipo de montaje | — | Surface Mount |