EPM5130LC vs EPM5130JC-1 Comparison
Detailed side-by-side comparison of EPM5130LC by Altera and EPM5130JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130LC | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $9.25 |
| Series | MAX 5000 | β |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| User I/O Pins | 48 | β |
| Total Inputs (Dedicated + I/O) | 68 | β |
| Dedicated Inputs | 19 | 19 |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| Maximum Internal Clock Frequency | 50 MHz | β |
| Global Clock Inputs | 1 | β |
| Configuration Technology | UV-Erasable / OTP EPROM | β |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| I/O Standard | TTL-compatible | β |
| Package | JLCC-68 (J-Lead Ceramic Chip Carrier) | 84-pin PLCC (J-lead) |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 2,500 gates |
| Maximum Operating Frequency | β | 62.5 MHz |
| I/O Pins | β | 80 |
| Programming Technology | β | UV-erasable EPROM (quartz window) |
| External Clock Pins | β | 1 global clock |