EPM5130LC vs EPM5130JC-1 比較
詳細並排比較 EPM5130LC 由 Altera 與 EPM5130JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130LC | EPM5130JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| User I/O Pins | 48 | — |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | 19 |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | — |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| I/O Standard | TTL-compatible | — |
| 封裝 | JLCC-68 (J-Lead Ceramic Chip Carrier) | 84-pin PLCC (J-lead) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Maximum Operating Frequency | — | 62.5 MHz |
| I/O Pins | — | 80 |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |