EPM5130LC vs EPM5130JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130LC sa pamamagitan ng Altera at EPM5130JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130LC | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| User I/O Pins | 48 | — |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | 19 |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | — |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| I/O Standard | TTL-compatible | — |
| Packhaging | JLCC-68 (J-Lead Ceramic Chip Carrier) | 84-pin PLCC (J-lead) |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial/military grade] | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Maximum Operating Frequency | — | 62.5 MHz |
| I/O Pins | — | 80 |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |