EPM5130LC vs EPM5130QC-1 Comparison
Detailed side-by-side comparison of EPM5130LC by Altera and EPM5130QC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130LC | EPM5130QC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $9.95 |
| Series | MAX 5000 | β |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | β |
| User I/O Pins | 48 | β |
| Total Inputs (Dedicated + I/O) | 68 | β |
| Dedicated Inputs | 19 | β |
| Propagation Delay (tPD) | 55 ns | β |
| Maximum Internal Clock Frequency | 50 MHz | β |
| Global Clock Inputs | 1 | β |
| Configuration Technology | UV-Erasable / OTP EPROM | β |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | β |
| I/O Standard | TTL-compatible | β |
| Package | JLCC-68 (J-Lead Ceramic Chip Carrier) | PQFP-100 (windowed ceramic) |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | Commercial (0 C to +70 C) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: rohs status] |
| Product Type | β | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Cells / Macrocells | β | 128 macrocells |
| Usable Gates (marketing) | β | 5130 gates |
| Speed Grade | β | -1 |
| Terminal Pitch | β | 0.635 mm |
| Configuration Memory | β | UV-Erasable EPROM |
| Supply Voltage | β | 5 V (single) |
| Programmable Polarity | β | Yes (per macrocell) |
| Boundary Scan / JTAG | β | Per MAX 5000 family |