EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera
MPN: EPM5130QC-1 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM5130QC-1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5130QC
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5130QC-2
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5128QC-1
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5130JC-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.25 / Unit
View Datasheet βEPM5130LC
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$15.6 / Unit
View Datasheet βEPM5130GM883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$108 / Unit
View Datasheet βEPM5130QC-1 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD (CPLD) |
| Logic Cells / Macrocells | 128 macrocells |
| Usable Gates (marketing) | 5130 gates |
| Speed Grade | -1 |
| Package | PQFP-100 (windowed ceramic) |
| Terminal Pitch | 0.635 mm |
| Process Technology | CMOS |
| Configuration Memory | UV-Erasable EPROM |
| Supply Voltage | 5 V (single) |
| Operating Temperature | Commercial (0 C to +70 C) |
| Programmable Polarity | Yes (per macrocell) |
| Boundary Scan / JTAG | Per MAX 5000 family |
| Mounting Type | Surface Mount |
EPM5130QC-1 Pin Configuration
| Pin 1 | I/O β User I/O - macrocell pin |
| Pin 2 | I/O β User I/O - macrocell pin |
| Pin 3 | I/O β User I/O - macrocell pin |
| Pin 4 | I/O β User I/O - macrocell pin |
| Pin 5 | I/O β User I/O - macrocell pin |
| Pin 6 | I/O β User I/O - macrocell pin |
| Pin 7 | I/O β User I/O - macrocell pin |
| Pin 8 | I/O β User I/O - macrocell pin |
| Pin 9 | I/O β User I/O - macrocell pin |
| Pin 10 | I/O β User I/O - macrocell pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O - macrocell pin |
| Pin 13 | I/O β User I/O - macrocell pin |
| Pin 14 | I/O β User I/O - macrocell pin |
| Pin 15 | I/O β User I/O - macrocell pin |
| Pin 16 | I/O β User I/O - macrocell pin |
| Pin 17 | I/O β User I/O - macrocell pin |
| Pin 18 | I/O β User I/O - macrocell pin |
| Pin 19 | I/O β User I/O - macrocell pin |
| Pin 20 | I/O β User I/O - macrocell pin |
| Pin 21 | I/O β User I/O - macrocell pin |
| Pin 22 | I/O β User I/O - macrocell pin |
| Pin 23 | I/O β User I/O - macrocell pin |
| Pin 24 | I/O β User I/O - macrocell pin |
| Pin 25 | I/O β User I/O - macrocell pin |
| Pin 26 | I/O β User I/O - macrocell pin |
| Pin 27 | I/O β User I/O - macrocell pin |
| Pin 28 | I/O β User I/O - macrocell pin |
| Pin 29 | I/O β User I/O - macrocell pin |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O - macrocell pin |
| Pin 32 | I/O β User I/O - macrocell pin |
| Pin 33 | I/O β User I/O - macrocell pin |
| Pin 34 | I/O β User I/O - macrocell pin |
| Pin 35 | I/O β User I/O - macrocell pin |
| Pin 36 | I/O β User I/O - macrocell pin |
| Pin 37 | I/O β User I/O - macrocell pin |
| Pin 38 | I/O β User I/O - macrocell pin |
| Pin 39 | I/O β User I/O - macrocell pin |
| Pin 40 | I/O β User I/O - macrocell pin |
| Pin 41 | I/O β User I/O - macrocell pin |
| Pin 42 | I/O β User I/O - macrocell pin |
| Pin 43 | I/O β User I/O - macrocell pin |
| Pin 44 | I/O β User I/O - macrocell pin |
| Pin 45 | I/O β User I/O - macrocell pin |
| Pin 46 | I/O β User I/O - macrocell pin |
| Pin 47 | I/O β User I/O - macrocell pin |
| Pin 48 | I/O β User I/O - macrocell pin |
| Pin 49 | I/O β User I/O - macrocell pin |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O - macrocell pin |
| Pin 52 | I/O β User I/O - macrocell pin |
| Pin 53 | I/O β User I/O - macrocell pin |
| Pin 54 | I/O β User I/O - macrocell pin |
| Pin 55 | I/O β User I/O - macrocell pin |
| Pin 56 | I/O β User I/O - macrocell pin |
| Pin 57 | I/O β User I/O - macrocell pin |
| Pin 58 | I/O β User I/O - macrocell pin |
| Pin 59 | I/O β User I/O - macrocell pin |
| Pin 60 | I/O β User I/O - macrocell pin |
| Pin 61 | I/O β User I/O - macrocell pin |
| Pin 62 | I/O β User I/O - macrocell pin |
| Pin 63 | I/O β User I/O - macrocell pin |
| Pin 64 | I/O β User I/O - macrocell pin |
| Pin 65 | I/O β User I/O - macrocell pin |
| Pin 66 | I/O β User I/O - macrocell pin |
| Pin 67 | I/O β User I/O - macrocell pin |
| Pin 68 | I/O β User I/O - macrocell pin |
| Pin 69 | I/O β User I/O - macrocell pin |
| Pin 70 | I/O β User I/O - macrocell pin |
| Pin 71 | VCC β +5 V supply |
| Pin 72 | I/O β User I/O - macrocell pin |
| Pin 73 | I/O β User I/O - macrocell pin |
| Pin 74 | I/O β User I/O - macrocell pin |
| Pin 75 | I/O β User I/O - macrocell pin |
| Pin 76 | I/O β User I/O - macrocell pin |
| Pin 77 | I/O β User I/O - macrocell pin |
| Pin 78 | I/O β User I/O - macrocell pin |
| Pin 79 | I/O β User I/O - macrocell pin |
| Pin 80 | I/O β User I/O - macrocell pin |
| Pin 81 | I/O β User I/O - macrocell pin |
| Pin 82 | I/O β User I/O - macrocell pin |
| Pin 83 | I/O β User I/O - macrocell pin |
| Pin 84 | I/O β User I/O - macrocell pin |
| Pin 85 | I/O β User I/O - macrocell pin |
| Pin 86 | I/O β User I/O - macrocell pin |
| Pin 87 | I/O β User I/O - macrocell pin |
| Pin 88 | I/O β User I/O - macrocell pin |
| Pin 89 | I/O β User I/O - macrocell pin |
| Pin 90 | I/O β User I/O - macrocell pin |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O - macrocell pin |
| Pin 93 | I/O β User I/O - macrocell pin |
| Pin 94 | I/O β User I/O - macrocell pin |
| Pin 95 | I/O β User I/O - macrocell pin |
| Pin 96 | I/O β User I/O - macrocell pin |
| Pin 97 | I/O β User I/O - macrocell pin |
| Pin 98 | I/O β User I/O - macrocell pin |
| Pin 99 | I/O β User I/O - macrocell pin |
| Pin 100 | I/O β User I/O - macrocell pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5130QC-1 is suitable for 6 applications: Industrial Control Glue Logic, Address Decoding for Microprocessor Systems, Peripheral Bus Bridge / Glue Logic, Telecommunications Equipment Interface Logic, State-Machine Replacement in Embedded Controllers, Educational and Prototyping Lab Platforms.
Industrial Control Glue Logic
The EPM5130QC-1 serves as high-density glue logic in industrial control boards, replacing dozens of 22V10/26V12-era PAL/GAL devices with a single 128-macrocell CPLD. Its UV-Erasable EPROM configuration lets field engineers iterate firmware during long commissioning cycles, while its deterministic propagation delay ensures predictable response for safety interlocks and sensor-conditioning logic. Compared with later FPGAs, the MAX 5000 CPLD boots in microseconds without external configuration memory, ideal for PLC backplanes where the controller must be live within milliseconds of power-up. The 100-pin PQFP provides ample I/O for parallel sensor buses, encoder interfaces, and opto-isolated control lines typical of industrial cabinets.
Recommended
Address Decoding for Microprocessor Systems
The EPM5130QC-1 is an ideal address decoder for legacy 80x86, 68k, and embedded ARM7/ARM9 systems where full-address-space decoding of memory-mapped peripherals, boot ROM, and dual-port RAM is required. With 128 macrocells, the device can decode a 24-32 bit address bus plus chip-select outputs for 8-16 peripherals in a single package. The MAX 5000 family's fixed-OR-array architecture delivers constant propagation delay across all input combinations, eliminating the decoding-glitch hazards that plague cascaded discrete PALs. The PQFP-100 footprint supports ample I/O for address, chip-select, and qualified-read/write signals on VME, ISA, or PC/104 buses.
Recommended
Peripheral Bus Bridge / Glue Logic
In peripheral bus bridges the EPM5130QC-1 implements protocol conversion between legacy buses (ISA, PCMCIA, parallel port, I2C/SPI expansion) and modern microcontrollers. Its 5130 usable gates and 128 macrocells are sufficient to build full hand-shake sequencers, FIFO control logic, and bus-arbitration state machines that previously required multiple discrete PLDs. Compared with FPGA-based bridges, the MAX 5000 CPLD offers faster power-on-to-active timing because no configuration flash is needed, which is critical in interrupt-driven USB or PCMCIA controllers where the host expects the peripheral within microseconds of insertion.
Recommended
Telecommunications Equipment Interface Logic
The EPM5130QC-1 historically served telecommunications chassis as the central glue-logic device for E1/T1 framers, HDLC controllers, and TDM cross-point switches. Its CMOS EPROM-based macrocells provided the deterministic timing required for telecom-grade bit-error-rate budgets while supporting the field-reprogrammability demanded by carrier-grade service loops. The 100-pin PQFP delivered enough I/O to bridge parallel DSP buses, line-interface unit serializers, and timing-reference distribution within a single device. For modern replacements, MAX II / MAX V CPLDs offer similar density at lower standby current, but legacy telecom boards remain in active service using the EPM5130QC-1.
Recommended
State-Machine Replacement in Embedded Controllers
The EPM5130QC-1 is well suited to replacing discrete TTL/CMOS state machines in embedded controller boards, where a single CPLD replaces 5-10 packages of 74LS/74HC flip-flops, decoders, and muxes. With 128 macrocells the device can implement multi-state sequencers for motor control, HVAC damper logic, or elevator call dispatch. The UV-Erasable EPROM storage means firmware can be revised by re-exposing the quartz window to UV light - a key benefit during long product lifecycles where field-installed hardware is updated in place. The PQFP-100 pin count comfortably supports 24-32 I/O signals plus internal feedback for state register expansion.
Recommended
Educational and Prototyping Lab Platforms
The EPM5130QC-1 is a classic teaching platform for digital-logic laboratories because its UV-Erasable EPROM allows students to repeatedly program, test, erase, and re-program the same chip across multiple lab sessions. With 128 macrocells and 100 PQFP pins, students can implement complete designs ranging from traffic-light controllers to UARTs and VGA signal generators on a single device. The windowed ceramic package also makes the chip a teaching tool for the EPROM programming model, which underpins later EEPROM/Flash-based PLDs (MAX 7000, MAX II) and FPGAs. Universities and vocational training labs continue to use the EPM5130QC-1 in introductory VLSI design and computer-architecture courses.
Recommended
Recommended Products Summary
Engineering reference data for EPM5130QC-1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5130QC | EPM5130QC-2 | EPM5128QC-1 | EPM5130JC-1 | EPM5130LC | EPM5130GM883B |
|---|---|---|---|---|---|---|---|
| Package | PQFP-100 (QC, windowed ceramic) | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same | PQFP-100 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Family | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Usable Gates | 5130 | 5130 | 5130 | 5128 | 5130 | 5130 | 5130 |
| Speed Grade | -1 | Standard | -2 (slower) | -1 | -1 | Standard | Military |
| Configuration Memory | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM | UV-Erasable EPROM |
| Operating Temperature | Commercial (0 to +70 C) | Commercial | Commercial | Commercial | Commercial | Commercial | Military (-55 to +125 C) |
| Package Code | QC (windowed ceramic PQFP) | QC | QC | QC | JC (plastic J-lead) | LC (plastic LCC) | GM (ceramic military) |
Key Differentiators
- Top-of-family MAX 5000 device with 5130 usable gates (vs EPM5128QC-1)
- -1 speed grade for tighter timing budgets (vs EPM5130QC-2)
- Windowed ceramic PQFP for repeated UV erasure (vs EPM5130LC)
- Commercial temperature range, broadest deployment (vs EPM5130GM883B)
Design Notes
Place decoupling capacitors (0.1 uF ceramic) as close as possible to every VCC and GND pair (pins 11/30/50/71/91 on the PQFP-100). Add a bulk 10-47 uF tantalum or low-ESR electrolytic within 25 mm of the device to suppress VCC transients during simultaneous macrocell switching. Use a solid ground plane on the layer beneath the package; the MAX 5000 family is sensitive to ground bounce on shared return paths. Estimated: with 128 macrocells switching simultaneously at 5 V, peak transient current can reach 200-300 mA; decoupling budget of 0.1 uF + 10 uF is sufficient.
Route I/O signals to inner PCB layers first, keeping critical clock and chip-select traces on the top layer with controlled impedance (50 ohm nominal). Assign macrocell feedback paths on dedicated tracks to avoid cross-talk with adjacent I/O; macrocell pin assignments can be locked in the Altera MAX+PLUS II fitter to prevent last-mile reroute shifts. Reserve a quartz-window socket footprint if UV erasure is anticipated for prototype iterations; for production, solder the PQFP-100 directly to the PCB.
Do not assume all unused I/O pins default to high-impedance - configure them in the MAX+PLUS II project as outputs with output-enable disabled, or tie them through 10 kohm resistors to avoid floating inputs. UV erasure requires 20-30 minutes of 254 nm exposure at 12-15 mW/cm^2; insufficient erasure will cause unreliable reprogramming. Avoid mixing TTL and CMOS input thresholds on the same device without consulting the datasheet; the MAX 5000 has separate input-threshold modes that must be selected at compile time. Estimated: threshold shift after 5 years of UV exposure retention at room temperature is negligible if the quartz window remains covered by an opaque label.
Compliance Information
RoHS/REACH status not documented in the verified web data; the windowed ceramic PQFP historically contains lead and other materials that may be non-RoHS. AEC-Q100 not applicable - this is a commercial-grade legacy CPLD. Confirm compliance directly with the broker/distributor for each date code.
