EPM5130WC-1 vs EPM5130JC-1 Comparison
Detailed side-by-side comparison of EPM5130WC-1 by Intel and EPM5130JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 Obsolete
Specification Comparison
| Parameter | EPM5130WC-1 | EPM5130JC-1 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Manufacturer | Altera (now Intel) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocell Count | 128 | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Propagation Delay (tpd) | 40 ns | — |
| Maximum Clock Frequency | 50 MHz | — |
| Erasure Method | UV (ultraviolet, windowed package) | — |
| Process Technology | CMOS EPROM | CMOS |
| User I/O Pins | Up to 100 | — |
| Package Type | 100-pin Ceramic QFP (Windowed) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Voltage | [DATA_NEEDED: VCC nominal] | — |
| Programmable | Yes (UV-erasable, non-volatile) | — |
| Logic Family | MAX 5000 (Altera) | — |
| Configuration Memory | EPROM (on-chip) | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Family | — | MAX 5000 |
| Usable Gates | — | 2,500 gates |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tPD) | — | 40 ns |
| Supply Voltage (VCC) | — | 5 V |
| Dedicated Inputs | — | 19 |
| I/O Pins | — | 80 |
| Package | — | 84-pin PLCC (J-lead) |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |