EPM5192AJC84-20 vs EPM5192ALC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJC84-20 by Altera and EPM5192ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoleteSpecification Comparison
| Parameter | EPM5192AJC84-20 | EPM5192ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | UV-Erasable/OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| Maximum Clock Frequency | 66.7 MHz | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | — |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS |
| Package | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Operating Temperature Grade | Commercial | — |
| Mounting Type | Surface Mount (J-Lead) | Surface Mount (PLCC socket-compatible) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in provided web data] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | Altera MAX 5000 |
| Speed Grade | — | -20 (20 ns pin-to-pin delay) |
| Terminal Pitch | — | 1.270 mm |
| Terminal Form | — | J-bend |
| Package Code | — | QCCJ (PLCC-84) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Family | — | MAX 5000 EPLD |
| I/O Compatibility | — | TTL-compatible |
| Configuration Memory | — | EPROM (UV-erasable) |